Quantus under the chip-case method

The tile

• Name: Quantus
• Subtitle: QPoW, Poseidon2, none built
• The big figure: 47x (the model's band 23x to 62x)
• What your card keeps: 2% (the band 1.6 to 4.3%)
• Grade: modelled, none built

The tile paragraph, in the chip page's form: "47x: a chip earns this many times your card for the same electricity, by the model (the band 23x to 62x). What your card keeps, next to the modelled chip: 2% (modelled, none built)." The stat line: "47x | Quantus, QPoW, Poseidon2, none built".

The definitions, the same as the five entries served

The big figure is how many times a chip earns the card's pay for the same energy on the same work: the chip's hashes per joule over the reference card's hashes per joule on that chain's own hash.

The reference card is the RTX 4090 at the public table's row. The percentage is what the card keeps next to the chip: one over the big figure. The grades are the comparisons record's: a shipped chip's spec-sheet figure against the public GPU table is SPEC SHEET; a figure the audit computed from published inputs is DERIVED; a chip nobody has built is MODELLED, none built, the Ravencoin row's grade. Every outside figure below carries its URL and the date it was read.

The work

QPoW as the chain's code defines it (qpow-math/src/lib.rs in the Quantus-Network/chain repository, read 18 October 2026, https://raw.githubusercontent.com/Quantus-Network/chain/main/qpow-math/src/lib.rs): the 32-byte block hash and a 64-byte nonce are concatenated (96 bytes) and hashed once by a Poseidon2 sponge with a double squeeze to a 512-bit output; the nonce is valid when the output, read as a 512-bit integer, is under the target (U512::MAX divided by the difficulty). The code's own comment calls it a single Poseidon2 hash with double squeeze; the site's subtitle carries the code's words, Poseidon2 with a double squeeze, not the pool guides' "double Poseidon2".

The sponge (qp-poseidon, src/poseidon2.rs and src/serialization.rs, read 18 October 2026, https://raw.githubusercontent.com/Quantus-Network/qp-poseidon/main/src/poseidon2.rs and https://raw.githubusercontent.com/Quantus-Network/qp-poseidon/main/src/serialization.rs): the Goldilocks field p = 2^64 - 2^32 + 1; state width 12, rate 8, capacity 4; 8 external (full) rounds and 22 internal (partial) rounds, the S-box x^7; bytes enter the sponge at 4 bytes a field element with a terminator element; each squeeze yields 4 elements (32 bytes). The round numbers match Plonky3's Goldilocks Poseidon2 at width 12 (8 full, 22 partial; https://raw.githubusercontent.com/Plonky3/Plonky3/main/goldilocks/src/poseidon2.rs, read 18 October 2026).

Permutations a nonce: 96 bytes make 24 elements plus the terminator, 25 elements at rate 8, so four absorbing permutations, then one more for the second squeeze: five. The earliest absorbs the block hash alone (its 32 bytes are exactly 8 elements, one rate block), so its result is the same for every nonce and any miner computes it once a block: four permutations a nonce for GPU and chip alike.

Multiplies a permutation: the 8 external rounds apply the S-box to all 12 elements and the 22 internal rounds to one, 118 S-boxes; x^7 costs four field multiplies (x^2, x^3, x^4, x^7), 472 full multiplies; the internal diffusion matrix multiplies the 12 elements by its diagonal constants in every internal round, 264 constant multiplies; the external matrix is additions. About 740 modular multiplies a permutation, about 2,950 a nonce. The Goldilocks reduction is shifts and adds (the prime's form), no division.

The inputs with their sources

The public GPU table (Kryptex pool device pages, read 18 October 2026; community-reported rates and software-read power, REPORTED):

The brief's figure of about 1.39 GH/s for a 5090 is below the Kryptex row (1.81 GH/s); the 4090's row is the reference either way. The pool's guide names SRBMiner-MULTI as the miner and says the algorithm maps well onto CUDA (https://pool.kryptex.com/articles/how-to-mine-quantus-en, read 18 October 2026); the network's rate was 25.70 TH/s on 9 October 2026 by the same pool's hashrate page (https://pool.kryptex.com/de/qtc/hashrate, read 18 October 2026).

The card's cross-check: the 4090's integer peak is 41.3 INT32 TOPS at 450 W (the Ada whitepaper, appendix A, https://images.nvidia.com/aem-dam/Solutions/geforce/ada/nvidia-ada-gpu-architecture.pdf, read 18 October 2026). At 1.35 GH/s that is 30,600 32-bit integer operations a nonce, about ten for each of the 2,950 64-bit modular multiplies (a 64 by 64 product is four 32-bit products plus the reduction's shifts and adds). The card is at its integer peak on this work: the chip's gain is the energy of a multiplier, not a mismatch of the work to the card.

The multiplier's energy (Horowitz, Computing's energy problem, ISSCC 2014, figure 1.1.9, rough energy costs in 45 nm at 0.9 V, https://www.gwern.net/doc/cs/hardware/2014-horowitz-2.pdf, read 18 October 2026): a 32-bit integer multiply 3.1 pJ, a 32-bit add 0.1 pJ, an 8 KB cache read 10 pJ.

The arithmetic

The chip (MODELLED): a fully pipelined permutation, one round a stage, 30 stages of 12 by 64 bits, one nonce a clock a pipeline, the state never leaving the pipeline (no memory, the only memory the round constants).

• A 64-bit multiply has four times the partial products of a 32-bit one: about 12 pJ at 45 nm by the figure above. A mature node (5 to 7 nm) takes eight to ten times off: the cross-check is Bitcoin's S21 XP Hyd at 12 J/TH, 12 pJ a double SHA-256 of about a thousand 32-bit add-equivalents and their registers, 0.01 pJ an add-equivalent against Horowitz's 0.1 pJ at 45 nm (the S21 figures on the comparisons record). That puts a 64-bit multiply at 1.2 to 1.5 pJ; with the Goldilocks reduction and the pipeline registers taken as a 1.3x to 2x overhead, 1.5 to 3 pJ a full multiply, the central 2 pJ, and half that for a multiply by a constant.
• A permutation at the central figures: 472 x 2 pJ + 264 x 1 pJ = 1,208 pJ, plus a quarter for the additions, the external matrix, the sponge and the clock tree: 1.5 nJ. A nonce, four permutations: 6.0 nJ, 166 MH/J.
• The low case (1.5 and 0.75 pJ): 4.5 nJ a nonce, 221 MH/J. The high case (4 and 2 pJ): 12.1 nJ, 83 MH/J.
• The edge over the 4090's 3.55 MH/J: the central 47x, the band 23x to 62x, served as the model reads them. The keep: 2.1%, the band 1.6 to 4.3%.
• The scale, for the reader: at 6 nJ a nonce one pipeline at 1 GHz is 1 GH/s at 6 W; a 3 kW chip is 500 pipelines, 500 GH/s, a fifth of the whole network's 25.7 TH/s of 9 October from one box.

The two figures with their grade

• The big figure: 47x (23x to 62x). MODELLED, none built: no Quantus chip exists; the figure is the audit's model on the chain's own code and a published multiplier energy.
• The keep: 2% (1.6 to 4.3%): one over the edge.

The FPGA stage

MODELLED. A Goldilocks multiply on DSP blocks: a 64 by 64 product needs about twelve 27 by 18 DSP slices. A Virtex UltraScale+ VU9P has 6,840 DSP slices (the maker's figure as listed by S2C, https://s2cinc.com/products/fpga-prototyping/logic-system-vu9p/, read 18 October 2026), about 570 full-rate multipliers; at 500 MHz that is 2.85 x 10^11 multiplies a second, about 97 MH/s at 2,950 multiplies a nonce, and a board of that class draws 60 to 100 W flat out: 1.0 to 1.6 MH/J, 0.3x to 0.45x of the 4090. By this model the FPGA stage reads under the card: the multiplies are DSP-bound and the fabric's static draw is paid whether or not the DSPs are busy. The precedent is Ethash's and KawPoW's: no FPGA ever served on a multiply-bound or memory-bound hash at a card's energy. An FPGA built from LUT multipliers raises the rate and the draw together; no public QPoW FPGA figure exists on the record (none found on 18 October 2026).

The precedent: kHeavyHash

Kaspa's kHeavyHash was mined on cards before any chip; the 4090 read 2,430 MH/s at 256 W at the high overclock on 21 April 2023 (https://www.kryptex.com/overclocking/nvidia-rtx-4090-micron-24gb-high-overclock, read 15 October 2026 on the comparisons record and again 18 October 2026), 105 J/GH; the Bitmain KS5 Pro of March 2024 reads 21 TH/s at 3,150 W, 0.15 J/GH (https://www.asicminervalue.com/miners/bitmain/antminer-ks5-pro, the comparisons record's read of 15 October 2026): 702x, the figure served as 700x. Why QPoW's band is tens and not hundreds: kHeavyHash's matrix step is 4-bit work the card runs on 32-bit lanes and its two Keccak passes are logic a chip does for almost nothing; SHA-256d is the same story at 3,413x. Poseidon2 over Goldilocks is 64-bit multiplies the card already runs on its native integer units at its peak, so a chip wins only the multiplier's energy and the memory traffic the card no longer has, not a shape mismatch. The band is where Ethash's stacked class (6x) and SHA-256d (thousands) are not: a chip that takes the whole work at tens of times a card.

The verdict under the increment rule

The goal of record's test is whether a complete specialist implementation saves too little to justify building and buying it; the method is the chip-case column and the increment rule (S-02).

On QPoW the specialist saves about 98 percent of the energy by this model, the Kaspa pattern at a smaller multiple: a chip is justified, and the chain's resistance rests on nobody having built one yet, not on the work's shape. The KS5 class followed kHeavyHash's cards by about a year after that 4090 row. No complete-cost column is computed here (no chip's bill exists); the energy edge alone is disclosed, as the goal requires.

The limits of the estimate

• The multiplier energy is a 45 nm figure scaled by a cross-check on another chip, not a placed design; the band 23x to 62x carries that, and a 5 nm design with a Montgomery-free Goldilocks reduction and clock gating could sit at the top of it or above.
• The GPU row is community-reported and tuned (REPORTED); a better CUDA kernel moves the 4090's figure, but the integer-peak cross-check says there is at most a third left in it.
• The multiply count takes x^7 at four multiplies and the diagonal matrix as constant multiplies; a chip may fold the constants into shift-and-add networks, which lowers its energy and raises the edge.
• No Quantus chip or FPGA exists on the record; the figure is a model and is served as one, with the words none built.
• No price, no earnings: hashes a joule only.