IgneumHash, the relation
What IgneumHash is
IgneumHash is Igneum's proof-of-work relation; the form on this page is its version 8, the item-as-programme form. It is a memory walk with a programme inside it. A miner holds a dataset (2 GiB at the gate cells, the launch default) and walks it: each step fetches an item that depends on the one before. No prediction shortcut has passed the registered attack tests; the million-nonce distribution and grinding rows remain part of qualification. Rate is set jointly by the dependent memory walk and the programme executed from each fetched item. The addition is that the fetched item is itself the programme the lane runs next: a block of single-precision operations with fixed rounding on every opcode, a cross-lane class in which lanes exchange values through the register crossbar, a 16-register lane window (the record writes the gate form as (2, 16)), and fixed per-item quotas on the opcode classes. Fixed quotas remove opcode-count variation; the registered grinding tests determine whether any residual cheap-item selection remains.
There is no generator. The earliest measured rows of the design showed that a programme generated from the item cost fourteen times the walk, so the item is the programme. On the measured gate cell the walk's normalised share of the energy reads 0.21 to 0.24 and the parts cost more than the whole: the walk-only and programme-only rows, measured on a 5090 at the same cap, clocks and thermal state, sum to 1.15 of the full form against the 0.70 line the auditor set. The verifier recomputes one item's programme and reads inside 2 ms on the node's path.
Every implementation is exact against one scalar reference and one frozen vector set per gate document (every registered gate document, every class, generated and self-tested). The rule for every vendor's kernel is one shared source text: no runtime-indexed private array and no conditional expression inside a hash routine, with per-machine exactness sets on every supported compiler class. The specification is linked from this page the day its public URL is named.
Why the current model predicts a smaller specialist edge
A chip built for a plain memory walk is a memory board: a controller, a bus and the memory of least cost that holds the dataset. The record's class ruling of 10 October 2026 read such boards, for the rejected predecessor relation (a plain memory walk, not IgneumHash), at about 3.9x a 5090 for an external-memory board and about 7.8x for a hybrid-bonded stacked-memory device, and the stacked device failed the launch line. That reading stands on the record as the predecessor's; it is why the relation changed.
The item-as-programme relation still performs the memory walk. Each fetched item also defines programmable lane work, so a specialist must provide both the dependent memory path and a programmable lane array. A shipped bonded-memory stack has no lane array and cannot run the programme. The chip that can is a new GPU-class die with no incumbent: on the record's supply model, 35 to 150 million USD of non-recurring engineering and 24 to 36 months to volume (Hypothesis on every chip term). On the captured trace the red team's cycle-level reconstruction found that a single lane runs at 0.20 utilisation, because the item fetch (90 to 240 cycles) dwarfs the block's 32 cycles; reaching 0.98 needs eight interleaved contexts and a 128-entry register file per lane, which is dearer per access than the 16-entry floor the extreme figure assumed. So the chip's two favourable assumptions cannot hold at once, and the strongest jointly feasible design is the figure of record.
| reading | figure | grade | what the grade rests on |
|---|---|---|---|
| the strongest jointly feasible specialist, programme-wide registered figures | 2.59x central, 3.25x governing upper | model | the specialist side is a placed reconstruction on the captured trace with the register terms on the published record; the GPU side under it is measured (board power) |
| the same at the 5090's 450 W operating row of record | 2.38x central, 2.96x upper | model | the specialist side; the GPU row under it is measured |
| the published register-file band | 3.15x upper | model | published latch-array register-file models, normalised to the record's process |
| every published term cut by half at once | 3.70x | model | a sensitivity, not a reading |
| the earlier 5.54x extreme | retained only as an incompatible-corner sensitivity | model | it needs a 16-entry register file's energy at the same time as the 128-entry file that full utilisation requires |
| AMD's own specialist table on the 9060 XT stand-in | about 3.0x central, 3.5x governing upper | model | model-derived from the AMD cell |
The auditor's registered sentence on the specialist side, held, with the internal code name replaced by the public name: "On IgneumHash's measured GPU trace, the specialist reconstruction reads 2.59x centrally and 3.25x at the governing jointly feasible upper. Published register-file models produce a 3.15x upper, while an additional simultaneous 50 percent attacker-favourable stress reads 3.70x. Every construction remains inside the registered 4x central and 5x upper coexistence limits." And: "These specialist figures remain modelled pending an external placed design."
What that shows: the strongest jointly feasible specialist reconstructed in the current model reads 2.59x centrally and 3.25x at the governing upper, with the simultaneous 50 percent-favourable sensitivity of 3.70x beside it. That is comparable with late-Ethereum coexistence ratios (a chip at 4.3x the then-current card held ten months with no rule change; the 2.5 to 5.5x band, Reported); that precedent does not guarantee Igneum's outcome and is context only. What it does not show: that no such chip is built, nor that a built chip reads what the model says, nor what any party could build. The specialist side is a model until an externally placed design exists, and the figure is a property of the relation, read again at every successor.
The three-vendor reading, with its boundaries
The auditor's cohort sentence, in the form it permitted on 11 October 2026: "NVIDIA and AMD board-power telemetry at the IgneumHash gate point differs by approximately 1.2x. Apple's rate is measured and its projected energy falls in the same range, but Apple has no device-power reading; its energy remains model-estimated until measured at the wall."
That sentence is never a wall-power comparison. The three halves are read on different instruments and the page says which.
| vendor | card | the row | what the instrument is | energy grade | state |
|---|---|---|---|---|---|
| NVIDIA | RTX 5090 (rented, 500 W cap) | 40.6 MH/s, 12.2 uJ per accepted hash at the gate point; the programme's energy 16.5 percent lower at the 450 W knee | board power, telemetry grade | measured | the energy row of record; stable repeats and the production parity row retained as requirements |
| AMD | RX 9070 XT (the card of record) | 13.92 uJ per hash at the gate point across two exact windows on the snapshot kernel, 1.14x the 5090 pod | board telemetry | measured | AMD family qualification passed at telemetry grade; wall confirmation remains |
| AMD | RX 9060 XT (the corroboration) | 14.0 to 14.3 uJ per hash across two windows, 1.16x the 5090; exact and spill-free on every class; the four snapshot-kernel windows across both cards within 2.5 percent | board telemetry | measured | independent RDNA 4 corroboration of the card of record |
| Apple | M6 mini (16 GB) | 1.97 MH/s at the gate point, double the earlier Metal kernel; thirty leak-free warm transitions at 2 GiB | rate measured; energy an estimate from a package band with no device reading | estimated | provisional product pass at 2 GiB; energy estimated until a plug on the mini |
| Apple | M5 Max (64 GB) | 5.4 MH/s at the gate point against 2.8 on the earlier kernel | rate measured; energy estimated | estimated | open: its own kernel work, its soak and full-battery repeat |
| NVIDIA | RTX 2060 | an unresolved IgneumHash result, kept visible | board power | pending | a cohort row, not a passed card and not a launch gate |
The auditor's AMD wording, held: "IgneumHash's corrected RDNA4 kernel provisionally passes the registered vendor-relative efficiency condition on the RX 9060 XT: 14.24 uJ per accepted hash, 1.17x the recorded 5090 pod cell and inside the walk's existing AMD differential. The result is exact and spill-free but remains provisional pending its repeat and direct RX 9070 XT confirmation."
The original AMD kernel failed as an implementation, not as a relation: the one kernel construct that had cost AMD 3.4x and Apple half their rate (a chain of selects serving a runtime register index) was removed from the shared source, and the snapshot kernel corrected that implementation cost. Nothing about the relation changed; the improvement from the original kernel to the card-of-record row is a kernel correction and is not to be read as a changed relation. The original kernel's row stays on the record as a superseded implementation control, failed. The production worker's old default tune was superseded the same morning; release parity applies only to the corrected knee configuration. The wider 32-register window was tried on every vendor and rejected for the gate relation: it did not win on all three, and the preregistered rule requires it to.
What is measured and what is not
- Measured: the GPU rows on NVIDIA and AMD (board power and board telemetry), the exactness of every implementation against the reference, the verifier's time, the overlap efficiency of the walk and the programme (1.15, above the 0.70 line), the register pressure (90 registers, no spills), the per-nonce timing spread (0.14 on every form and size, the memory walk's own latency; the programme's variance under 1 percent, abort unprofitable).
- Estimated: Apple's energy per hash, until the plug on the mini gives a wall figure. No Apple row carries a power reading.
- Model: every specialist figure, pending an external placed design.
- Pending, in the auditor's words: "Arithmetic programme grinding is closed by construction; the empirical million-nonce timing and early-abort distribution remains pending." The measured spread rows are on the record and the qualification stays until the auditor lifts it.
The auditor's wording for the whole, held
Captured on the morning of 11 October 2026, with the internal code name replaced by the public name; the route decision later that morning does not change it: "IgneumHash now has exact implementations across NVIDIA, AMD and both tested Apple compiler classes. NVIDIA's efficient point models at 2.38x central and 2.96x governing upper, with conservative registered figures of 2.59x and 3.25x. The corrected AMD kernel provisionally passes the vendor-relative condition on an RX 9060 XT stand-in across repeated windows. Apple's snapshot kernel doubles the previous Metal implementation, and the M6 mini has completed thirty leak-free warm transitions at 2 GiB; Apple energy remains estimated pending a wall measurement, while M5 Max optimisation remains open. A CUDA worker has entered IgneumHash warm with zero boundary downtime or invalid work, subject to the recorded 12% preparation cost and a successful return at height 6370. The overall result remains provisional pending that return, the RX 9070 XT, stable production-worker repeats, Apple wall power and M5 Max closure."
The return at 6370 stored correctly and the warm GPU-worker round trip reads final on the tested pair, in both directions, with the disclosed 12 percent rate reduction during the 32-block preparation window. AMD family qualification passed on the RX 9070 XT at telemetry grade later the same morning; wall confirmation remains. The rest of the list is open and stays open on this page until the record closes it.
Where the figures come from
Every figure on this page names a row in the record: the auditor's gate verifications of 11 October 2026 (gates 1 to 11), the morning brief of that day, the launch text, the specification and the frozen vector sets. Each is linked from this page the day its public URL is named; the rows you can read without this site are listed on Verify it yourself.