Pearl under the chip-case method

The tile

• Name: Pearl
• Subtitle: pearlhash, FP8 GEMM, the H100 class
• The big figure: 3.9x to 6.1x (the H100 3.9x, the B200 6.1x)
• What your card keeps: 16 to 26%
• Grade: spec sheet; on the miners' own rows the chips read 1.2x today

The tile paragraph, in the chip page's form: "3.9x to 6.1x: a chip earns this many times your card for the same electricity, by the makers' FP8 spec sheets (the H100 3.9x, the B200 6.1x). What your card keeps, next to the strongest chip: 16 to 26% (spec sheet; on the miners' own rows the chips read 1.2x today)." The stat line: "3.9x to 6.1x | Pearl, pearlhash, FP8 GEMM, the H100 class". The work's name on the whitepaper's page: E4M3FN (FP8) matrix multiplication, as the whitepaper states.

The definitions, the same as the five entries served

The big figure is how many times a chip earns the card's pay for the same energy on the same work: the chip's work a joule over the reference card's work a joule, at the precision the chain's hash runs at.

The reference card is the RTX 4090 at the public table's row and at its maker's spec-sheet figure for the same precision. The percentage is what the card keeps next to the chip: one over the big figure. The grades are the comparisons record's: SPEC SHEET where a shipping part's maker gives the figure; REPORTED for the public GPU tables and the miners' own release notes; DERIVED where the audit divided published figures; MODELLED where the audit extrapolates. Every outside figure carries its URL and the date it was read.

The work

Pearl's whitepaper (Pearl Floating Point Scheme Specification, Pearl Research Team, September 2026, https://pearlresearch.ai/Pearl_Whitepaper.pdf, read 18 October 2026) states the unit of mining work as FP8 matrix multiplication on GPUs: the operands are quantised to FP8 E4M3FN after low-rank noise (rank r = 32) is added, the product is accumulated in FP32 by the whitelisted GPU's own tensor arithmetic (the accumulator's internal precision named by architecture: 13 mantissa bits on Hopper, 25 on Blackwell; summation in groups of 32), each output tile's FP32 bit patterns are folded by an extractor and hashed with BLAKE3 into a 32-byte ticket, and the tile wins when the ticket is at or below the target scaled by the tile's work. The dimensions are public, with 1 <= m, n <= 2^24 and 1,024 <= k <= 2^16; the Device and the Quant are each chosen from a consensus-allowed list, and Device names the GPU architecture because E4M3FN operands alone do not fix a bit-exact result. Work is counted in multiply-accumulates: the tile's cost is |IA| x |IB| x k MACs, which fixes the scale only. The pool guide says the algorithm relies on tensor cores (https://pool.kryptex.com/articles/how-to-mine-pearl-en, dated 15 September 2026, read 18 October 2026). The underlying paper is Komargodski and Weinstein, Proofs of Useful Work from Arbitrary Matrix Multiplication (https://arxiv.org/abs/2504.09971, April 2025, revised November 2025, read 18 October 2026), with 1 + o(1) overhead over a plain multiply.

So the work is dense FP8 GEMM with FP32 accumulation on NVIDIA tensor cores, by the chain's own specification. The useful part is the shape of the arithmetic only: the network multiplies whatever matrices the miner chose; no buyer orders the products and none receives them.

The inputs with their sources

The public GPU table (Kryptex pool device pages, read 18 October 2026; community-reported rates and software-read power, REPORTED; the pool's unit is TH/s, terahashes a second, and the pages do not say whether a hash is one MAC or one floating-point operation):

A second public table (Miningboard, updated October 2026, https://miningboard.com/guides/how-to-mine-pearl-coin, read 18 October 2026) lists the 4090 at 220 TH/s at 380 W (0.579 TH/W) and the 5090 at 305 TH/s at 500 W (0.610): the Kryptex row is the row of record here, the second table beside.

The miners' own rows (REPORTED by the miner's author): SRBMiner-MULTI 3.6.1 names a B300 SXM6 at about 706 TH/s at 920 W at a 1,600 MHz core clock (https://newreleases.io/project/github/doktor83/SRBMiner-Multi/release/3.6.1, read 18 October 2026), 0.767 TH/W; the 3.6.2 note improves pearlhash for the H100, H200, B200 and 4000 series; 3.7.2 to 3.7.6 (6 to 14 October 2026) make new kernels the default on Ampere, Ada and Blackwell (https://github.com/doktor83/SRBMiner-Multi/releases, read 18 October 2026). The hashrateindex note of 2 June 2026 says the official pool accepts only H100 and H200 cards, the community pools consumer cards (https://hashrateindex.com/blog/pearl-prl-ai-compute-cryptocurrency/, read 18 October 2026).

The card's cross-check: the 4090's dense FP8 tensor peak is 330.3 TFLOPS with FP32 accumulate and 660.6 with FP16 accumulate at 450 W (the Ada whitepaper, appendix A, https://images.nvidia.com/aem-dam/Solutions/geforce/ada/nvidia-ada-gpu-architecture.pdf, read 18 October 2026). At 293 TH/s the card is at 89 percent of a dense peak either way: of 330.3 if a hash is one floating-point operation, of 660.6 if a hash is one MAC (then 586 TFLOP/s, above the FP32-accumulate peak, so the kernel would be on the FP16-accumulate path). The card is at its tensor peak on this work, as the chain intends.

The spec sheets at the chain's precision, FP8 dense (every NVIDIA data-centre figure is published with sparsity and halved here for dense, as the makers' footnotes say):

The matrix ASICs: Google's TPU v4 is 275 TFLOPS BF16 or INT8 a chip at a measured 170 W mean and 192 W maximum running production work (Jouppi and others, TPU v4, https://arxiv.org/abs/2304.01433, table 4, read 18 October 2026); the v5e 197 TFLOPS BF16 and 393 TOPS INT8 a chip and the v6e 918 TFLOPS BF16 and 1,836 TOPS INT8, neither with a published watt figure; Google states the v6e at 4.7 times the v5e's peak compute a chip and 67 percent better energy efficiency (https://cloud.google.com/blog/products/compute/trillium-tpu-is-ga/, 11 December 2024, read 18 October 2026) and Ironwood at 4,614 TFLOPS FP8 a chip at twice Trillium's performance a watt (https://blog.google/products/google-cloud/ironwood-tpu-age-of-inference/, 9 April 2025, read 18 October 2026), again without watts.

The arithmetic

At the chain's precision, FP8 with FP32 accumulate, DERIVED from the spec sheets:

• The H100 SXM: 2.83 over 0.734 = 3.85x; the card keeps 26%.
• The H100 NVL: 4.18 over 0.734 = 5.7x; 18%.
• The B200: 4.50 over 0.734 = 6.1x; 16%. The whole DGX box with its hosts and fans: 2.52 over 0.734 = 3.4x.
• If the kernel is on the FP16-accumulate path (the 4090's 660.6, 1.468 TFLOPS a watt): the H100 1.9x, the B200 3.1x. The whitepaper's accumulator is FP32, so the 0.734 row is the reference and the FP16 row the lower bound.

The miners' own rows, REPORTED, against the 4090's Kryptex row: the B300 at 0.767 TH/W is 1.18x; the GA100 mining card 1.23x; the 5090 1.17x. The shipped kernels on the data-centre parts read near 1.2x today where the spec sheets read 3.9x to 6.1x; the gap is the kernels' (the B300 figure is an earliest-release row, the 3.7 series' kernels are days old), not the silicon's, and the chain's whitepaper counts the H100 and B200 class as the intended miners.

If pearlhash were BF16 on tensor cores (it is not; for the matrix ASICs, which have no FP8 before Ironwood and are outside the chain's Device list): the 4090's dense BF16 is 165.2 TFLOPS at 450 W, 0.367 a watt; the TPU v4 at 192 W is 1.43 a watt, 3.9x (4.4x at its 170 W mean); the H100 3.85x; the B200 6.1x. MODELLED: the v6e at 4.7 times the v5e's rate and 1.67 times its efficiency, and Ironwood at twice that again, would read in the B200's band or above it, but no watt figure is published for either and the chain's arithmetic is not theirs.

If pearlhash were plain FP32 without tensor cores: the 4090's 82.6 TFLOPS at 450 W is 0.184 a watt against the H100's 67 at 700 W (0.096) and the B200's 75 at 1,000 W (0.075): the data-centre parts would read under the card, 0.5x and 0.4x, and a dedicated FP32 GEMM chip would be a model on no shipped part. The FP32 tensor path (TF32) returns the H100 to 3.85x (494.5 dense at 700 W against the 4090's 82.6 dense). The chain chose FP8 on tensor cores, so these two lines are what the choice forgoes, stated for the reader.

The two figures with their grade

• The big figure: 3.9x to 6.1x, the H100 at 3.85x and the B200 at 6.1x. SPEC SHEET: shipping parts, the makers' dense FP8 figures with FP32 accumulate against the 4090's maker figure at the same precision; the B200's watt figure from a listing of the maker's TDP. The miners' own rows read 1.2x today, REPORTED, beside.
• The keep: 16 to 26%: one over the edge.

The FPGA stage

No row. An FPGA must reproduce the whitelisted device's accumulation bit for bit (the whitepaper's Device enumeration names GPU architectures and their accumulator precision), so a Pearl FPGA miner is a reproduction of a named GPU's arithmetic before it is a miner; no public pearlhash FPGA figure exists on the record (none found on 18 October 2026), and no adaptive-SoC maker's FP8 spec sheet was opened for this page, so no figure is given rather than one from memory.

The precedent

Ethereum's Ethash: the stacked-memory class at 6.0x on the comparisons record (the Jasminer X16-Q against the 4090's ETChash row), the external-board class 3.3x.

Pearl's data-centre class sits in the same band by the spec sheets, with one difference: Ethash's chips were built for the chain by two makers over years; Pearl's chips were built for AI by NVIDIA and Google before the chain existed, ship in volume, and the chain names them as the intended miners. The strongest shipping class is the miner class by design, so the card's keep is the spec-sheet ratio from day one, and a consumer card runs the same arithmetic at a lower rate a watt.

The verdict under the increment rule

The goal of record's test asks whether a complete specialist implementation saves too little to justify building and buying it.

On pearlhash the specialist already exists and is bought for other reasons: the H100 and B200 save 74 to 84 percent of the energy a card spends by their spec sheets, and the chain's whitepaper and official pool are built around them. There is no increment to measure on the chain's side; the chip case is the makers' catalogue. The useful work is the arithmetic's shape only (no buyer, no delivered product), so the chain's pay goes to whoever holds the most FP8 tensor throughput a watt, which is the accelerator's whole purpose.

The limits of the estimate

• The hash unit (MAC or FLOP) is not published; the 89 percent cross-check holds under either reading, and the big figure is a ratio of spec sheets at one precision, so the unit cancels.
• The spec sheets are peak dense figures at the maker's TDP; a mining kernel's share of peak differs by part (the 4090 at 89 percent, the B300 by its miner's own row far lower), and the B200's TDP is a listing of the maker's figure, not read from the maker's page.
• The miners' own rows are REPORTED and move with each release (seven pearlhash releases between 19 September and 14 October 2026).
• The TPU lines are MODELLED on Google's relative claims with no published watts, and TPUs are outside the chain's Device list; they are given for the reader of the chip case, not as a Pearl figure.
• No price, no earnings: work a joule only.