Chip resistance, as measured

This page serves the chip claim in the words the record supports and nothing stronger. Every figure below names its adversary, its column (energy, capital, cost ratio), its clock state (knee or stock), the card, the adversarial set version and the file it comes from. The GPU side is measured. Every chip figure is a WITNESS: a design that was priced and found to cost at least that much less, never a ceiling on what a better design could do. Nothing here is a pass against a target. Where a row has not run it says so.

The record lives in the repository under docs/analysis/class-v6/1p5x/ (the laboratory interface lab/README.md, the scoreboard lab/table.md, the adversary lane's rows under lab/adv/). The paths on this page name the files on the repository's master as of 14:0x UK on 9 October 2026 (the scoreboard at commit a61a487e9); rows still on the adversary lane's branch are named with their branch and commit. The public git host serves a path once its copy of master carries it.

1. The claim

The current model finds that existing GPU electricity costs are below the assessed DRAM-board specialist's all-in costs at the tested tariffs and stated lifetime assumptions. This supports a conditional entry-deterrence result. It does not yet establish post-deployment competitiveness, viable GPU replacement or new entry, or coexistence against the modelled SRAM fleet at sufficient scale. Those outcomes remain separately assessed.

That is the approved wording (lab/README.md section 8c, item 9). The sentence the rows support today, in plain words: a DRAM-board chip can be built, and it does not undercut a card its owner already has at the three tested electricity tariffs; the chip that stores the whole dataset on its die is the residual, held by its project cost and the growth schedule, and it is examined below with its break-even fleet. The position line of the Token Value volume stands beside it: Igneum is designed to compete for leadership among GPU-first networks; what has been demonstrated is named on this page, nothing more.

The supported headline (main's ruling of 14:4x UK, 9 October 2026, on the laboratory's rows), verbatim: "the only live GPU network whose GPUs earn income a chip cannot (LIVE on Devnet 4: one epoch, 928 shard and 86 aggregation records, 1,453.53 IGN to 15 prover keys, 51 percent of the pool's credit), with the chip-to-GPU edge of every live chain measured the same way on the same cards and published with its attacker". The approved conditional wording above stays the claim's frame; the headline rests on the proving record in section 7 and on the five-chain session in section 4, and it ranks nothing by a word: the measured order under our convention is served as numbers only.

Labels used on this page: MEASURED (a card on a pod or rig, board power read from the driver), WITNESS (a chip design priced as a complete machine; at least this advantage exists), BOUND (a limit no design of the class can beat), MODELLED (an assumption, with its source), PROXY (a stand-in row until the pinned control is measured), PENDING, NOT RUN, BLOCKED and NOT LIVE.

2. The measured card rows

The object is the frozen class v6 signing program at 2^30 dataset words, 4 GiB (the dataset word 1,073,741,823 on every self-test), the public Linux CUDA worker, board power from the driver, stock clocks (every rented container refused a clock lock), the median of three timed runs, the fingerprint equal on every cell. The rows are summarised on the scoreboard's ctl-v6 row (lab/table.md, the cohort cell); the raw rows with their checksums sit on the build host under the lab's artefact tree, named by pod.

What the rows mean for an owner: at stock a 5090 spends about 6 microjoules on every hash, a 4090 about 8.7, a 3090 about 12; the card's memory path takes 81 to 86 percent of that energy on the uncapped cells (the read-only twin kernel at the same rate; x7/README.md), which is why no rewrite of the arithmetic moves the ratio much.

Not measured, said plainly: AMD (RX 7600 to 9070) and Intel Arc tiers NOT RUN (no rented card on either provider on 9 October; the project's own rigs unreachable by software that day; retried hourly). Wall power BLOCKED on every rented pod (no meter): board power only, the idle watts beside each row. Clock locks refused by every rented container, so the only knee row is the project's own 5090.

3. The same-node DRAM board, under our convention

Our convention: the cheapest programmable core a specialist would build, priced as a complete machine (its own GDDR7 board, controller, host share, power train and cooling), on the same process node as the card and one node ahead, with every instruction counted the way the chip executes it (the instruction convention; a counted-op row is never served alone). Adversarial set v3 (the adversary lane's routed fused-ARX lanes on ASAP7, the 64-register window and the fused multiply-xor pair routed at commit b2b9ee0b9; the frozen v6 board unchanged from set v2) (lab/adv/README.md, branch class-v6-adversary at commit 545f3f8a0); the figures as summarised on the scoreboard's ctl-v6 adversary cell.

The board's energy at the knee, split: the chip 527 nJ memory, 167 nJ arithmetic, 849 nJ fixed-function tax (1,543 nJ in all, band 1,328 to 1,947) against the card's 3,642 memory, 369 arithmetic, no tax. The tax ladder states what the chip's own overhead is worth: 2.60x with the record's static tax, 3.28x at half of it, 4.43x at none (the BOUND for this design).

3a. Two measured verdicts on the search for a better object

4. Both conventions, side by side

Two conventions exist for the same question and give different numbers. Ours is above: the cheapest programmable core, complete machine. ProgPoW's premise is that a chip must keep a GPU-class datapath to run the work, so its edge is what it saves by leaving out the parts of a GPU it does not need; the published ProgPoW estimate under that premise is 1.1x to 1.2x. Every served ratio carries both.

The two conventions do not disagree about the hardware; they disagree about what the specialist is allowed to build. Under ProgPoW's premise the column cannot separate the chains: on each cell's measured memory share f every memory-bound chain reads 1.00x to 1.05x, this network's work among them, because the card is already spending nearly all of its energy on memory it cannot avoid; under ours the same card loses 2.6x at its knee to a chip with its own memory board, because a GPU's random-read path costs 4x to 13x what a chip's does per read (x7/README.md). Under our convention, measured the same way on the same cards, the order at the clean RTX 5090 reads as numbers (the laboratory's five-chain session of 9 October 2026, main's ruling of 14:4x UK; the scoreboard carries the rows): Ravencoin 3.25x, Igneum 4.37x, Ethereum Classic 7.27x (the shipped E9 Pro chip at 9.3x), Iron Fish 7.60x; each chain's attacker is the cheapest design the adversary lane priced for its work, published with the row. The per-chain rows on this page change from PROXY and PENDING to measured as the scoreboard carries each pinned control's cohort row with its band.

5. The coexistence table

Energy alone does not say who mines. The coexistence table prices the chip as a machine against a GPU owner who already has the card (its capital sunk), at the three tested tariffs. Source: the adversary lane's coexistence rows and price sheet (lab/adv/README.md sections 6 and 7, commit 545f3f8a0), as summarised on the scoreboard's ctl-v6 coexistence cell. Assumptions, all MODELLED and stated on the rows: a 100,000-machine fleet, a 24-month straight-line life, a design cost of USD 35 M for the board chip and USD 300 M for the reticle die (both claimed brackets taken at a point), the card sunk at USD 30.6 per MH/s on class v6 at the knee, GDDR7 at USD 20 per 2 GB device (September 2026), the core at USD 0.36 per mm2 of N5, the three tested tariffs USD 0.05, 0.10 and 0.15 per kWh.

The last column is the cost ratio: the chip's all-in cost per terahash over the GPU owner's electricity-only cost per terahash. Above 1.0 the owner's card keeps mining beside the chip; below 1.0 the owner's electricity alone exceeds the chip's whole bill.

The itemised phase B bill for the board at ten cents, per terahash: electricity 0.043, capital 0.141, design share 0.081, hosting 0.009, maintenance 0.014; in all USD 0.288 against the GPU owner's 0.111, cost ratio 2.58. The die's bill 0.037, cost ratio 0.34 (lab/adv/README.md section 11).

What this table does not say: it compares the chip with a card already owned. It is a conditional entry-deterrence result, nothing more; the phases below say what happens once a chip exists.

6. The new buyer and the used card

A new buyer compares the chip's all-in with a new card's all-in (street price over the same 24 months plus electricity). On the record the new buyer picks the chip on every row and every tier at ten cents: the same-node board costs 0.34x a new 5090 at the knee (street USD 42.7 per MH/s), 0.31x a 5090 at stock, 0.24x a 4090, 0.43x a 5080; the hybrid 0.22x; the die 0.04x. The card price at which a new buyer is indifferent: USD 9.7 per MH/s on the 5090 at the knee, 10.5 on the 5080, 5.4 on the 5090 at stock, 2.6 on the 4090. The one hold is the maker's project share: below about 13,500 boards sold the USD 35 M design cost keeps a new buyer on a new 5090; above it the chip (lab/adv/README.md section 8).

The used card does not close that gap: a used 4090 at USD 1,200 or a used 3090 at USD 700 (claimed, October 2026) with 40 percent of the price kept as resale at 24 months, against a chip whose resale is zero after a program-draw change, still loses to the board at ten cents (the 3090: the chip at 0.45x; indifferent at USD 2.0 per MH/s); the fleet at which the maker's design share stops holding the used-card buyer is about 20,000 machines for the 3090 and 16,000 for the 5080. Memory growth closes the new-buyer gap only at about 227 GB of dataset, outside every schedule to month 72.

So the honest reading of this section: the installed base holds at the three tested tariffs; a new buyer is held only while the chip maker's fleet is under about 13,500 boards (14,300 dies).

7. The two phases

The fifth review ruled that the coexistence table proves conditional entry deterrence only, and ordered the question split into two phases per adversary (lab/README.md section 8c, items 5 and 11). Rows: lab/adv/README.md section 12, branch class-v6-adversary at commit 36d17b15c, every row WITNESS; the adversary lane's landings on master (82330b04c, d7db3e596) are in their gates, and this page cites the rows at master once they are there. Sources on the rows: the 80/20 split of each block's subsidy (80 to the producer, 20 to the proving escrow) from the Token Value volume's D02 record (docs/plans/igneum-2.0-master/token-value/phase0/d02/README.md, sha256 e4292764…) and the node's PROVING_POOL_SHARE_PERCENT; the year-1 subsidy 963,038,999.99 IGN from TV-04; three price paths with their hashrates from the coexistence model (growing: doubling from USD 0.10 at 20 TH/s; flat: USD 0.10 at 6.9 TH/s; falling: halving from USD 0.30 at 1.7 TH/s).

Phase A, before investment: can the maker recover its spend? The fleet is added to the chain's hash and earns the mining share of the emission at the path's mean price over 24 months, electricity at ten cents; the spend is the fleet's capital plus the design cost.

In words: a maker's spend comes back only where the chain is small and the price high enough for a few thousand boards to take a third of it; on the growing and flat paths of record no maker recovers. This is the row behind "conditional entry deterrence".

Phase B, the spend sunk: who exits first? Once the chip exists its maker ignores the sunk capital and compares operating cost alone. On operating cost the board chip beats the GPU owner (its electricity, hosting and maintenance about USD 0.066 per TH against the owner's 0.111), so on hash income alone GPUs exit first as revenue falls or difficulty rises. The sixth review adopted the hardware split as the answer: a GPU earns the mining share plus the proving share of each block, a hash chip the mining share only, since a chip that proves is a GPU.

LIVE ON THE DEVNET; not yet in a shipped package. The proving lane's record, verbatim: "On the Igneum 2.0 devnet (chain id 4465), over one epoch (chain blocks 32,000 to 33,534, 12:02 to 13:00 UTC on 9 October 2026), the project's fleet of 24 GB GPUs proved shards beside their miners and was paid the proving share from the pool: 928 shard records and 86 aggregation records, 1,453.53 IGN to 15 prover keys (14 RTX 4090s, one L40S), 51 percent of the 2,850 IGN the pool was credited at the ratified 20 percent of block subsidy, with 60 percent of chain blocks carrying a paid shard proof; read from the node's proving-status, segment-record and block calls. Live on the devnet in the fleet's prover stack; not yet read from a shipped package." Record: lab/proving-live.md (the epoch ledger file beside it in the lab artefact tree, sha256 2b657227…). What that means for the row: the proving income the phase B rows assume is paid on the devnet today, by the project's own fleet; the Mac and Windows apps turn the prover on by default on an NVIDIA card of 24 GB and above, the HiveOS package proves from the 2.0.3.1 package, and the 16 GB tier mines only. The "shipped package" clause clears when the proving lane reads the same record from a package an operator installed. The stated assumption on every phase B row: all proving stays on the GPU cohort; a chip maker who fields GPUs to prove is a GPU miner with a sidecar.

8. The residual: the die

The chip that stores the whole 4 GiB dataset on N2 reticles is the strongest design the record prices: 11.9x the 5090's energy at the knee, USD 1.59 of capital per MH/s, a cost ratio of 0.3x at ten cents. It is not held by energy and it is not held by the dataset's size: no growth schedule stops a 100,000-die fleet paying, and the break-even fleet rises only from 14,300 dies to 16,700 or 25,000 under the schedules (lab/adv/README.md section 9). What holds it is a project: USD 300 M of design and masks (claimed bracket USD 100 M to 500 M) against a chain whose whole mining emission over 24 months is USD 231 M at the growing path's mean price, so in phase A it recovers on no path at any fleet, and in phase B the ratified 20 percent proving share is exactly the share at which its operating advantage disappears. The die stays a live opponent in both phases on every row; where a row calls it implausible, the row names the assumption that fails (the project cost against the emission).

9. What is still open

10. The GPU network ledger

The GPU network ledger: every row and its record is the ledger lane's page beside this one: the same rows, each linked to its record and the reproduction kit, with each clause's state. This page serves the approved wording only; the ledger page serves its rows with their labels.

11. How to read a figure here, and how to reproduce one

A card figure is board power from the driver over the worker's accepted rate, the median of three timed runs on one pod, the fingerprint checked against the CPU reference; the raw rows carry the pod id, the driver, the power cap state and the dataset words. A chip figure is a placed-and-routed core on a predictive 7 nm-class library scaled on claimed node factors, its memory and machine terms from the price sheet, every assumption on its row; it is a witness of at least that advantage. A ratio is one card figure over one chip figure, named by both. The laboratory's rule, printed here as it is there: nothing on this page claims impossibility, and nothing on it claims inevitability. The reproduction kit for the frozen control (the 4 GiB packs, the read-only twin, the worker and the fixtures) is the lab's founder bundle, available on request through the Discord's #devnet channel until the public git host carries the record.