12 October 2026. A team seat, independent of the team seats that produced the clock on the record (an in-house adversarial review's simt-die.json and tapeout-schedules.json, ecosystem's supply model and SUPPLY-CORNERS.md, a team seat's band). Written against main at 98b5a317. Companion to review 1 (2026-10-12-redteam-specialist-edge.md), whose placed design is the frozen implementation this review takes to silicon. Earliest draft; no computation on a box was needed for it.
Grades as in review 1: MEASURED, DERIVED, ESTIMATED, ASSUMED, and REPORTED for a published figure not measured by the project (dates, prices, lead times), each with its source.
0. The verdict in six lines
- The record's 24-to-36-month lead is the design-to-volume of a GPU-class SIMT-lane die with 35 to 150 M USD of NRE and no incumbent (simt-die.json, LAUNCH-GUARDS.md G2, SUPPLY-CORNERS.md section 12). Review 1 finds that die is not the adversary: the frozen relation is served by a fixed round pipeline on a mature node beside commodity or bonded DRAM, the Ethash mining-ASIC class, which is a 100 to 450 mm2 die at 28 to 7 nm with 12 to 30 M USD of NRE (ESTIMATED, section 2).
- For that machine the design-start-to-volume clock is 13 / 17 / 24 months (strong / central / weak) for a well-funded new entrant building an external GDDR6 board with licensed PHY IP and no shortcuts; 10 / 14 / 20 months for the stacked-DRAM incumbent respinning its compute die on its own DRAM die and bonding line; 18 / 24 / 36 months for a new entrant that must also obtain a custom bond-interface DRAM die (ESTIMATED on the record's tape-out and Ethash schedule rows, section 3). Only the last route reaches the record's figure, and no attacker needs it.
- The strongest-case adversary with no silicon at all, an FPGA card with HBM2 (the Alveo U55C class), runs one pipeline of the relation at an estimated 2 to 4 uJ per hash, 3x to 6x the GPU row of record and 1.8x to 3.5x the 4090 knee, within 2 to 4 months of engineering and at about twice the GPU's capital per MH/s (ESTIMATED, section 3.4). It is economically marginal as a fleet and decisive as a demonstration: it is the artefact that turns review 1 from estimated to measured, for either side.
- Time to a third of the work on the record's own supply model (lead-bound at a third of the floor network, SUPPLY-CORNERS.md sections 2 and 3): the lead plus about a month: 14 / 18 / 25 months from the earliest actionable disclosure for the board, 11 / 15 / 21 for the incumbent. Against the locked schedule's exposure of 13 to 14 months (a 12-month entry, one to two months from disclosure to genesis) the board's central clears by 4 to 5 months and its strong edge sits at the line; the incumbent's central clears by one to two months and its strong edge fails by two to three (DERIVED, section 5).
- The 24-to-36-month lead does not survive. What survives: a 10-to-25-month band, central about 15 to 17 months, with the record's own exposure inside its lower half; the record's reading that the attacker is lead-bound and capital- cheap once it exists (the die costs a few USD per MH/s against the 5090's 49); and the observation that the clock is conditional on motive: a 20 M USD programme is started only for a network whose revenue repays it, which the Ethash precedent (the earliest board 35 months after launch, at 4.6 M USD per day of revenue; REPORTED) bounds from above, not from below.
- The most dangerous assumption in the record's clock is the adversary's die class (a GPU-class SIMT die). The most dangerous in this review is the engineering time of the random-access memory controller for a new entrant, the one part of the board the Ethash makers already own and a newcomer does not (section 6). The artefacts that would make this clock measured are a dated cost-and-schedule quotation from an ASIC design house for the pipeline with a GDDR6 PHY on a mature node, and the FPGA row.
1. The frozen implementation taken to silicon
Review 1 section 4: one compute die per 2 GiB dataset holding R round pipelines (one round per cycle per pipeline, 15.6 MH/s at 1 GHz), a context station of 5 to 10 MB, the memory controller and PHY, three BLAKE3 units, a scheduler and a host link; about 1.5 to 2.5 mm2 per pipeline at N7 (ESTIMATED). Three physical forms, in the order an attacker would choose them:
| Form | Die | Memory | Per-hash energy (review 1, central) | Who can build it |
|---|---|---|---|---|
| A: external board | 100 to 180 mm2 at N7, or 250 to 450 mm2 at 28 nm; a licensed GDDR6 PHY and controller; flip-chip BGA | commodity 16 Gb GDDR6 devices, one per 2 GiB engine, several engines per die, many dies per board | about 1.0 uJ (the engine 0.24 plus the board's 0.8 memory class) | any mining-ASIC vendor; the Antminer E9 and A11 Pro class of product |
| B: stacked incumbent respin | the same pipelines on a compute die bonded to the incumbent's existing bond-interface DRAM die (the DH40G class the TechInsights teardown names, REPORTED) | the incumbent's stack | about 0.57 uJ | the one or two vendors with a DRAM-to-logic hybrid-bonding product line in hand (the X4 and X16 makers) |
| C: new-entrant stack | as B, plus a custom DRAM die with a bond interface from a DRAM vendor and a qualified bonding line | about 0.57 uJ | a well-funded entrant with a DRAM partner |
The relation's own constants fix the memory per engine at 2 GiB (one 16 Gb GDDR6 device, or 2 GB of a bonded die), the random access rate at 64 activates per hash, and the bytes at 8 KiB per hash; the engine's compute is small beside the memory system in area and in cost on every form. Section 4 of review 1 and the record's stacked-machine file agree that the successors on the lifecycle menu (W256, 4 GiB, the state steps) are modes or capacity on the same die class, so the die is built once (the record's own invalidation reading; not re-derived here).
2. Cost: mask set and NRE, design and verification, packaging and memory (ESTIMATED; the class figures REPORTED)
| Driver | 28 nm | 16 / 12 nm | N7 | Basis |
|---|---|---|---|---|
| mask set and wafer NRE | 1.5 to 3 M USD | 4 to 8 M | 10 to 15 M | REPORTED class figures (foundry and design-house press, 2020 to 2026); the record's N5 reticle-class 30 to 60 M (sram_cost.json) is the next node up and not needed |
| licensed IP: GDDR6 PHY and controller (form A), or the bond-interface controller (B, C) | 2 to 5 M | 2 to 5 M | 3 to 6 M | REPORTED class (PHY vendors' licence plus royalty); form B's controller is the incumbent's own |
| design team: architecture, RTL, verification, physical design, DFT, firmware; 20 to 30 engineers for 12 to 18 months | 5 to 10 M | 6 to 12 M | 8 to 15 M | ASSUMED at 250 k USD per engineer-year loaded; the pipeline's RTL is small (the reference's C is the specification), the controller and the physical design are the work |
| EDA licences, emulation, test chips (a shuttle, section 3.3) | 1 to 3 M | 1 to 3 M | 2 to 4 M | REPORTED class |
| packaging and test NRE, board NRE, qualification | 1 to 2 M | 1 to 2 M | 1 to 2 M | REPORTED class |
| one respin reserve (a second mask set and four months; the A11 Pro's earliest-silicon slip is the precedent) | 1.5 to 3 M | 4 to 8 M | 10 to 15 M | the record's tapeout-schedules.json: the A11 Pro shipped at 1,500 against 2,000 MH/s after a three-to-seven-month slip (REPORTED) |
| TOTAL NRE, form A | 12 to 26 M | 18 to 38 M | 34 to 57 M | central about 20 M at 28 or 16 nm |
| form B (the incumbent: its PHY, its line, a compute die only) | 8 to 18 M | 12 to 25 M | 20 to 35 M | |
| form C (B plus a custom DRAM die with a bond interface and the line's qualification) | plus 2 to 8 M for the DRAM die (stacked-machine.json, Hypothesis there) and 3 to 10 M for the line |
Unit cost (ESTIMATED): a 300 mm2 die at 28 nm on a 3,000 USD wafer (REPORTED) at about 150 candidates per wafer and 70 to 80 percent yield: 25 to 30 USD; at N7, 150 mm2 on a 10,000 USD wafer, about 350 candidates at 80 percent: 35 USD; a 16 Gb GDDR6 device 8 to 12 USD (REPORTED class); a board of 32 engines with its PSU and cooling 1,200 to 1,800 USD for about 200 to 300 MH/s on the activate-rate-bound GDDR6 devices (6 to 9 USD per MH/s); the record's board row (230 USD per 200 MH/s, 1.15 USD per MH/s) and the E9's shipped price (14,000 USD per 2,400 MH/s, 5.8 USD per MH/s, REPORTED) bracket it. Against the 5090 at 49 USD per MH/s (the record) the capital edge is 5x to 40x; the attacker is never capital-bound, which is the record's own reading and carries.
3. Schedule: the phases, per route (ESTIMATED; the anchors REPORTED)
3.1 The anchors on the record
- The general custom-ASIC schedule (tapeout-schedules.json, REPORTED): design start to tape-out 9 / 15 / 24 months, tape-out to earliest silicon 3 / 4 / 6, earliest silicon to volume 2 / 4 / 9; total 14 / 23 / 39. That figure is for an arbitrary custom chip; the pipeline here is at the simple end (a fixed datapath, no caches, no cores, no software stack) and the memory controller at the demanding end (activate-rate-bound random 128-byte reads).
- The Ethash makers (the same file, REPORTED): announce to ship 2 to 15 months; earliest products 3 (E3), 7 (A11 Pro), 15 (E9); second products on a proven die 2 (A10 Pro, E9 Pro, X4). No maker published its design start. The earliest Ethash board of all, the E3, shipped 35.5 months after Ethash's launch (lane-nochip-timelines.json), when the chain paid 4.6 M USD per day; the makers who followed shipped new products within a year of each other.
- The stacked class (stacked-machine.json, Hypothesis there): the incumbent's compute-die respin to volume 9 / 15 / 30 months (the 9 for a respin on a mature node with the DRAM die and the line in hand; the 30 for a new entrant with the custom DRAM die); the bonding line is not the cap (a die-to-wafer bonder places 2,000 to 3,000 dies an hour).
- Foundry access (tapeout-schedules.json, REPORTED, a third-party tracker): N7 allocation lead 8 to 16 weeks and falling; N5/N4 22 to 32 weeks; N3 kick-offs suspended; N2 an 18-to-36-month engagement. Mature nodes do not bind.
3.2 Route A: a well-funded new entrant, the external GDDR6 board, no shortcuts
| Phase | Strong | Central | Weak | What sets it |
|---|---|---|---|---|
| architecture and RTL of the pipeline, the station, the scheduler; the reference's vectors as the testbench | 2 | 3 | 4 | the relation is fully specified and vectored; the pipeline is straight-line |
| the memory controller for 64 random activates per hash at the device's tFAW and bank limits; PHY integration | 3 | 4 | 6 | the hard part for a newcomer; the Ethash makers own one already (then 1 to 2) |
| verification, physical design, DFT, timing closure (overlapping the above by half) | 3 | 4 | 6 | |
| tape-out to packaged, tested earliest silicon | 3 | 4 | 5 | the fab cycle at 28 to 7 nm, packaging, test |
| bring-up, board and firmware, the respin risk | 1 | 2 | 4 | the A11 Pro precedent: an earliest-silicon trim or a respin |
| ramp to volume (the earliest thousand units a month) | 1 | 2 | 3 | the Ethash tails of 2 to 3 months |
| design start to volume, with the overlaps | 13 | 17 | 24 |
An existing mining-ASIC vendor (its controller, its board, its supply relationships in hand) reads 10 / 13 / 18 on the same table (ESTIMATED): the record's own "quickest design-start-to-volume on the record, 14 months" (SUPPLY-CORNERS.md section 1) is inside it.
3.3 Route B and C: the stacked class
- B, the incumbent's respin: RTL and the bond-side integration 4 / 6 / 8 months (its controller and PHY are its own; the pipeline is new and larger than Ethash's datapath); tape-out to silicon 3 / 4 / 5; re-bonding and qualification on the existing line 1 / 2 / 3; bring-up and ramp 2 / 2 / 4: 10 / 14 / 20 months to volume. The record's 9 / 15 is the same reading; this review's strong edge is a month longer because version 8's compute die is not a trivial respin.
- C, a new entrant with a DRAM partner: the custom bond-interface DRAM die 12 / 18 / 24 months in parallel with the compute die, the line's qualification 3 / 4 / 6 after both: 18 / 24 / 36 months. This is the one route that reaches the record's 24 to 36, and it is the route an attacker takes only if no incumbent sells the stack and no board is good enough; review 1 says a board at 6x to 22x is good enough.
A shuttle run (a multi-project wafer at 28 nm or 12 nm, 0.1 to 0.5 M USD, a 3-to-4-month cycle; REPORTED class) gives test silicon of the pipeline without the PHY at month 6 to 8 of route A; it de-risks the datapath and the station but does not shorten the volume clock, which runs on the full mask set and the controller. A prepared entrant validates on the FPGA instead (3.4) and goes to the full mask set directly.
3.4 The no-silicon adversary: an FPGA card with HBM2
The Alveo U55C class (16 GB of HBM2 at 460 GB/s, about 150 W, about 5,000 USD; 9,024 DSP slices at about 500 MHz; REPORTED class figures): the walk is activate-bound on HBM2's 32 pseudo-channels at about 3 to 4 G activates per second (ESTIMATED from the tFAW and bank counts), 45 to 60 MH/s per card; the pipeline's arithmetic at that rate (about 10^12 FP32 operations per second plus the integer cell and tree) fits in a fraction of the DSP array; the station in the card's SRAM. Energy 2 to 4 uJ per hash at 100 to 200 W (ESTIMATED): 3x to 6x the 5090 row of record and 1.8x to 3.5x the 4090 knee. Engineering: 2 to 4 months for a competent team (the reference C as the model, the vector sets as the testbench, the HBM controller IP supplied with the card). Capital about 100 USD per MH/s against the 5090's 49, so a fleet of them repays its extra capital only at tariffs above about 0.2 USD per kWh (DERIVED: the energy saving is about 0.5 to 2 USD per day per 50 MH/s against 2,500 USD of extra capital); as a fleet it is marginal, as a demonstration it is decisive, and as a strategic buy by a party that wants share rather than profit it is available at month 3.
4. Supply
| Term | Form A (board) | Form B (incumbent stack) | Form C (new stack) | Grade |
|---|---|---|---|---|
| wafers | 28 to 7 nm: allocation leads of weeks (N7 8 to 16 weeks); no engagement clock; the volume for a third of the floor network is hundreds of wafers a month at most | the incumbent's existing allocation | the same plus the DRAM vendor's | REPORTED (tapeout-schedules.json) |
| memory devices | commodity GDDR6, one 16 Gb device per engine; the GPU vendors' demand sets the price, not the availability (the 2021 to 2022 boards were built through a shortage) | the incumbent's DRAM die and line (the record: 20,000 stacks a month is about 60 DRAM wafers) | a custom DRAM die: the one true supply constraint, few vendors, 12 to 24 months | REPORTED class; the record's stacked-machine bonding figures |
| packaging | flip-chip BGA, commodity | die-to-wafer hybrid bonding on the existing line | a line to qualify, 3 to 6 months | REPORTED class |
| units a month at volume | thousands of boards (each 200 to 300 MH/s): the E9 class shipped in the thousands over months | the record's 3,000 to 100,000 stacks a month | the same after qualification | REPORTED class (ethash-ramp.json: units in the thousands to tens of thousands, unaudited) |
| the fill to a third of the work | days to weeks once volume starts (the record's supply model: lead-bound at every registered allocation; SUPPLY-CORNERS.md section 2: "the design-start-to-volume term decides the gate and nothing else in the model does") | the same | the same | the record's model, DERIVED there; this review does not re-run it and does not need to, because the die class does not change the conclusion that the attacker is lead-bound |
5. The lead against the exposure (DERIVED from sections 3 and 4 and the record's schedule)
T_33 = the design-to-volume lead from the earliest actionable disclosure + hosting (0 to 1 month) + the fill (weeks).
| Attacker | Lead to volume (months) | T_33 from disclosure (months) | Locked schedule, exposure 13 / 14 (12-month entry, 1 or 2 months to genesis): margin | Reading |
|---|---|---|---|---|
| form A, new entrant | 13 / 17 / 24 | 14 / 18 / 25 | +1 to 0 / +5 to +4 / +12 to +11 | the central clears by four to five months; the strong edge at the line |
| form A, an existing mining-ASIC vendor | 10 / 13 / 18 | 11 / 14 / 19 | -2 to -3 / +1 to 0 / +6 to +5 | the central at the line |
| form B, the stacked incumbent | 10 / 14 / 20 | 11 / 15 / 21 | -2 to -3 / +2 to +1 / +8 to +7 | the strong edge fails by two to three months, as the record's own section 7 found at its 9-month corner |
| form C, a new-entrant stack | 18 / 24 / 36 | 19 / 25 / 37 | +6 / +12 / +24 | the only row near the record's figure; not the route an attacker needs |
| the FPGA card (no silicon) | 2 to 4 | 3 to 5 | fails every schedule | but at a capital cost that no fleet pays for profit |
| THE RECORD: the SIMT-lane die | 24 / 30 / 36 | 28 to 30 at the attacker-favourable corner, never within 48 months at the central | +15 to +17 | the figure under review; it stands only for the GPU-class die |
Two notes on the clock's start. For one, the relation is already public: the specification is on a public repository, the reference and the vectors are published, and the development chains have sealed under the launch document since 11 October (RELATION-STATE.md); on the record's own definition (the earliest actionable disclosure P), the clock is running, and genesis sits at the "G minus P" end of the exposure, not at its start. Second, a motive clock sits in front of the engineering clock: the Ethash earliest board came 35 months after launch not because the chip took 35 months but because the revenue that justified it took that long to appear (REPORTED, lane-nochip-timelines.json); the record's economics (ADVERSARY-MODEL.md, the 100 k to 10 M USD per day sweeps) carry that, and a 20 M USD programme is started when a third of the work is worth more than that over the entry's life. At 1 M USD per day it is; at 100 k it is not. Containment by lack of motive is a property of the network's size, not of the relation.
6. Assumptions, ranked by how far each moves the clock
| Rank | Assumption | Grade | If wrong | By how much |
|---|---|---|---|---|
| 1 | the adversary's die is a fixed round pipeline on a mature node (review 1), not a GPU-class SIMT die | DERIVED from the relation | the record's 24 to 36 returns | the whole gap, 17 to 30 months at the central |
| 2 | a new entrant's time to a working activate-rate-bound memory controller and PHY integration (3 / 4 / 6 months, overlapping) | ESTIMATED | a newcomer without memory-system experience could take twice that; an Ethash vendor has it on the shelf | plus 3 to 6 months on form A for a newcomer, minus 2 to 4 for a vendor |
| 3 | one respin reserve, not two | ASSUMED on the Ethash record (one public earliest-silicon slip in six products) | a second respin adds 4 to 6 months and a mask set | the weak edge to 30 |
| 4 | mature-node foundry access does not bind | REPORTED (2026 lead times) | a return of the 2021 shortage adds a quarter | plus 3 months everywhere |
| 5 | the incumbent respins rather than waits | ASSUMED | an incumbent with no motive (section 5) never builds; one with a motive builds on the quickest row | the form B row exists only with a motive |
| 6 | the record's supply model's lead-bound reading (the fill in weeks) | the record's DERIVED | a smaller floor network makes the fill shorter still; a far larger one makes supply bind, which only lengthens T_33 | the band's upper edges, not its lower |
| 7 | the custom DRAM die at 12 to 24 months (form C) | the record's Hypothesis | a DRAM vendor with a bond-interface die in its catalogue shortens it to a purchase | form C collapses onto form B |
The single most dangerous assumption in the RECORD's clock is rank 1. The single most dangerous in THIS review is rank 2, the controller, because it is the one engineering term where a newcomer's and a vendor's clocks differ by months and the record holds no measured design time for any Ethash maker.
7. What would turn the clock from estimated to measured
- A dated cost-and-schedule quotation from an ASIC design house for the review 1 pipeline with a licensed GDDR6 PHY on 28 or 16 nm, with the respin terms named: the industry's ordinary pre-sales document, obtainable without disclosing the purpose beyond the datapath. It would replace sections 2 and 3.2 with REPORTED figures.
- The FPGA row (3.4): an implementation of one pipeline on an HBM card, exact on the vector sets, with a wall-meter reading. It measures the lower bound of the specialist's energy edge and dates the no-silicon adversary.
- For the stacked class, a vendor's lead time for a bond-interface DRAM die (a purchase enquiry), which pins form C's critical path.
- Observed manufacture cannot be produced by the project, as the independent reviewer said; but the earliest two artefacts are the project's to make and are what an independent reviewer would ask for before the rest.
8. What survives, said once
The record is right that the attacker, once it exists, is lead-bound and capital-cheap, and that the lead is the only containment the relation offers. It is wrong about the lead's length, because it priced a die the relation does not require. On this review the lead is 10 to 25 months with a central of 15 to 17, the locked schedule's exposure sits inside the lower half of that band, and the stacked incumbent's strong edge fails it by two to three months, which is the direction the record's own stacked-class reading (SUPPLY-CORNERS.md section 7) already pointed before it was superseded by the SIMT-lane die. Condition 2 reads, on this review: the modelled 24-to-36-month lead does not hold for the frozen implementation; a 10-to-25-month band holds in its place, with the assumptions of section 6 and the two artefacts of section 7 named.
9. Record: inputs, by path at main 98b5a317
the simt-die file, blend-machine.json, stacked-machine.json, tapeout-schedules.json, ethash-ramp.json, ethash-shipped-chips.json, historical-frontier.json, menu-lifetimes.json, invalidation-criterion.json, sram_cost.json, die_vs_board.json; the SUPPLY-CORNERS file (sections 1 to 4, 7, 8, 12, 12.1, 12.2); the CAPITAL file and SCALE.md (headings and the earliest tables); LAUNCH-GUARDS.md (G2); the 2026-10-12-closure-reading-4 file and -5.md; the redteam directory calibration/lane-nochip-timelines.json; the FORGE-B1-SPEC file section 9 (the adversary table, as a checklist of the forms); review 1 for the die. Class figures for mask sets, IP, wafer prices, FPGA cards and packaging are REPORTED from public industry sources as this review knows them in 2026 and are labelled so; none is a measurement. No em dash; no personal name; no box name; times UK.