The strongest feasible chip, reconciled

12 October 2026 (the coordinator's order on the project's word: "we cannot say we have 2 to 3x but a chip can be made at 9 to 10x"). The relation's owner's page, reconciled with an in-house adversarial review's and the edge adjudicator's independent ten-minute lines where they arrived by 19:00 (section 6 names what each said). Against main at 93f108954e3d. Nothing here is served; the project reads the page; the coordinator decides the served sentence.

Grades as in the answer: MEASURED, DERIVED, ESTIMATED, ASSUMED. The GPU row of record is the 5090 pod at 500 W, 12.206 uJ per hash on the blended relation and 2.844 uJ on the walk alone (MEASURED); the memory classes are the record's (the X16-Q bonded stack 326 nJ per hash whole-machine wall row, MEASURED class; the external boards 480 to 1,250 nJ, MEASURED class; the placed SRAM die 67 to 238 nJ central by process, the record's sram_machine rows, Hypothesis whole-machine).

0. The answer in five lines

1. No relation form on the record puts the strongest feasible specialist under 3x central or 5x upper against the 5090 row while the chain stays GPU-mined. The four new candidates (i) to (iv) fail on energy for the same reason the earlier four did: the GPU's energy per hash is bounded below by its own memory path and its SIMT issue, and a chip built for one relation pays neither; every lever that raises the chip's cost raises the GPU's faster (sections 1 to 4).
2. The true energy number against the strongest feasible chip is the bonded-stack class's: 6x to 9x on the walk (6.5x central at W256 on the adjudicator's per-activate scaling, 5.6x to 7.3x on the rows alone), and the SRAM-die class reads worse (tens, section 1), so "6x to 9x" is the number to serve, with the sentence that no GPU-mined relation reaches 3x against a bonded stack.
3. What the project can honestly claim under 3x is the external-memory board class (2.4x to 3.0x central at W256 on the shipped boards), which is the class any mining-ASIC vendor can build without hybrid bonding.
4. The levers that bound the stacked class are not energy: capital per hash (the X16-Q sold at 1,000 to 2,500 USD per 2 GiB stack, Reported; the record's stacked-machine capital row) and the clock (the development time to a placed, bonded, shipped machine, review 2's subject), read through the standard's economics guard beside G1.
5. The one class on the drawing board that reads under 3x central against every class on the record's own model is ProgPoW's (section 6): a per-period programme of register-wide integer arithmetic the miner compiles into the card's native instruction stream, which forces the chip to be a programmable core (the record's c band 1.3 to 4.0, central 2.16; ProgPoW's audits 1.2x to 2x): 2.5x central at the programme's share of 0.8 and 4.5x upper on the stacked class, at the price of the GPU's own number (the card at 5.6 to 14 uJ per hash, not R0C's 2.7). It is the candidate for R0D's rows tonight; R0C stays the walk-only control and the form that improves the GPU's number.

1. Candidate (i): a working set inside the GPU's own on-die cache (the 5090's 96 MB L2)

The form: a hot working set of 64 MB (inside the 96 MB L2) walked at random per round, with a larger cold dataset behind it for the item layout (an item's address drawn from the hot set's words, say one cold read per several hot reads).

The GPU's cost: an L2 hit on a 5090 costs about 0.5 to 1 pJ per byte at the cache (the record's energy-N3 and wire bands, ESTIMATED) plus the SM's request issue, against 2.5 to 4 pJ per byte for a GDDR7 read with its activate; so the hot walk's memory energy falls 3x to 5x per byte and the card's energy per hash is then its SIMT issue and the L2's tag and data arrays: of the order of 0.5 to 1.0 uJ per hash for 64 x 128-byte hot reads (DERIVED) plus whatever cold reads the layout forces. The card runs at its L2 bandwidth (several TB/s), so the rate rises several times. MEASURED nowhere; a cell is one night (the walk at a 64 MB dataset is one document parameter: dataset_mib 64).

The specialist's cost: a 64 MB working set is 512 Mbit, 21 mm2 of N7 SRAM at the record's 24.8 Mbit per mm2 (DERIVED from sram_machine.json): a small on-die array on the engine's own die, read at 0.05 to 0.15 pJ per bit placed (the record's SRAM terms, ESTIMATED), 5 to 15 pJ per 128-byte item, 0.3 to 1 nJ per hash for the hot walk; the cold dataset behind it on a bonded stack or a board at its measured class, read at the layout's rate. The engine's datapath is the walk's 0.03 to 0.1 uJ (an in-house adversarial review's terms) or the adjudicator's 0.05 to 0.6 uJ with the state movement. So the chip's energy per hash is 0.1 to 0.7 uJ against the card's 0.5 to 1.0: the edge is 1x to 7x, central about 2x to 3x ON THE HOT WALK ALONE. That is the one candidate that reads near 3x on paper, and it reads there because BOTH sides are SRAM-class and the ratio collapses toward the datapath's, as the coordinator's candidate says.

Why it fails as a relation: (1) the cohort. A 64 MB hot set is inside the 5090's 96 MB L2, the 4090's 72 MB, the 5080's 64 MB (at the edge), and NOT inside the 4070's 36 MB, the 3060's 3 MB, the 2060's 4 MB, the 9070 XT's 64 MB L2 (edge; its 8 MB of L3-class cache beside), the 9060 XT's 32 MB, the 7600's 32 MB, the 6600's 32 MB, the 580's 2 MB, the M6's and M5 Max's system caches (24 to 48 MB): the cards without the set on die read it from DRAM at the walk's full cost and the cohort's spread opens to 5x to 10x in energy per hash (DERIVED from the L2 sizes and the per-byte costs; the 8 GB cards are the losers), which breaks the cohort condition (within about 2x) harder than any specialist does. (2) The SRAM die. The record's sram_machine rows (SRAM-MACHINE.md) already read a 2 GiB dataset resident in SRAM at 67 to 238 nJ per hash whole-machine by process, and against the measured GPU anchors "the ratio is in the hundreds on every process, and against the 90 percent rows still in the tens"; a 64 MB hot set makes that die cheap (one die, 21 mm2 of array) and the ratio against the hot-walk card is the datapath ratio of section 1 above, 1x to 7x, because the card's L2 is its SRAM too; but the cold dataset behind the hot set is still a 2 GiB walk the layout forces at some rate, and the chip serves it from a bonded stack at 326 nJ per hash-equivalent while the 8 GB cards serve it from GDDR6: the cold term re-opens the stacked class's 6x to 9x on the cold reads' share. (3) The security of the walk: a 64 MB hot set is 2^19 items; the whole-item rule, S1 to S9 and the keyed form hold, but the memory-hardness that the standard's long-clock guard rests on (a chip must hold 2 GiB) is gone: the clock guard is re-read against a 21 mm2 array, which every process node makes in weeks.

Verdict: (i) reads 2x to 3x on the hot walk against the SRAM die and the stack alike, at the cost of the cohort (the 8 GB and small-cache cards fall 5x to 10x behind) and of the long-clock guard; it is not a GPU-cohort relation. If the board wants it sized on a card, the cell is dataset_mib 64 on the 5090 and the 3060, one night.

2. Candidate (ii): a dataset too large to stack economically (tens of GB)

The GPU's cost: the walk's energy per hash is the same at any dataset the card holds (the 4 GiB twin reads 3 percent under 2 GiB on the 5090, MEASURED; the row is activate-bound, not size-bound). The cohort: at 8 GiB the 8 GB cards fall out (the dataset plus the cache plus two epochs), at 16 GiB the 16 GB cards (the 5080, the 9070 XT, the 9060 XT, the 5060 Ti, the 4070 Ti class), at 24 GiB the 4090, at 32 GiB the 5090s and the M6 mini; the M5 Max at 64 GB and the data-centre cards remain. So "tens of GB" is a chain mined by 32 GB cards and the data-centre class: the cohort condition is broken before the stack is.

The specialist's cost: a bonded stack is 2 GiB per DRAM die (the UNIC DH40G class, Reported); the X16-Q's machine carried its DAG across eight stacks; a 16 GiB dataset is eight dies per engine and the capital per MH/s scales with the dies (the record's dataset-size rule: capital scales with the memory, energy per hash does not): 8x the capital per hash of the 2 GiB stack, which is 8 x 1,000 to 2,500 USD per engine (Reported class) at the same 326 nJ per hash. HBM3E on a logic die (the record's capacity-machines reading, 3.2 to 6.9x on the walk, ESTIMATED) holds 24 to 36 GB per stack today and is the specialist's answer to tens of GB; it is also exactly the data-centre GPU's memory, so the cohort that survives (H100 and MI300X class) and the specialist share the memory class and the edge collapses toward the datapath, 1.5x to 3x (DERIVED from the record's MI300X screening row at 11.73 uJ on the blended relation and the walk's share) at the price of a chain mined by data-centre parts.

Verdict: (ii) moves the claim from energy to capital (the economics guard reads capital per hash at 8 x the stack's) and empties the cohort; on energy the stacked class stays at 6x to 9x against the consumer cards that remain. The economics guard is the right instrument for the stacked class whatever the dataset size (section 5); the dataset size is not the lever that makes it so.

3. Candidate (iii): (i) and (ii) together

The hot set in the L2 gives the datapath ratio on the hot reads for the cards that hold the set (section 1); the cold dataset at tens of GB empties the cohort (section 2). The combination is the worst of both for the cohort and no better than (i) for the edge: the strongest feasible chip holds the hot set in 21 mm2 of SRAM and the cold set on stacks whose count the layout's cold rate sets. 2x to 3x on paper for a cohort of two cards. No.

4. Candidate (iv): a latency-bound dependent chain sized to the L2's latency

The form: a per-round dependent chain whose latency matches the L2's (about 200 to 300 ns on a 5090 for a dependent chain of L2 hits, ESTIMATED), so that a pipeline's context station must hold as many contexts as the GPU holds warps and be SRAM of the same size.

The GPU's cost: unchanged on energy (a dependent chain lowers the card's rate through occupancy, section 2 of the sizing; the card's energy per hash rises only through its idle power's larger share at a lower rate, about 10 to 30 percent at a 2x rate loss, DERIVED from the 5090's idle fraction at the cap).

The specialist's cost: the station is SRAM already (an in-house adversarial review's and the adjudicator's engines both hold the contexts in an SRAM or latch station of 5 to 10 MB for 8,000 to 15,000 contexts at the stack's latency); a chain at the L2's latency, shorter than the stack's random-read latency, needs FEWER contexts, not more: the station shrinks. Sizing the chain to the DRAM's latency instead (section 2 of the sizing) grows the station 3x in capacity at under 10 percent of energy. The GPU's warps are its station; both sides pay SRAM for contexts; the energy of the station is one write and one read of 512 bytes per round on both sides (the GPU's register file at 1 to 2 pJ per 32-bit access, the engine's at 0.1 to 0.4): the engine's is cheaper by the same factor as its datapath. No.

5. What is true, and what to serve

The number to serve: "a chip built for IgneumHash's walk reads 6x to 9x the energy efficiency of an RTX 5090 on a hybrid-bonded memory stack (the class one maker has shipped), 2x to 3x on an ordinary memory board, and more on a die that holds the whole dataset in SRAM; the project's containment is of the board class and of the clock and capital of the other two, not of their energy." The standard's G1 as written (the strongest jointly feasible specialist at or under 3x) is not met by any GPU-mined relation against the stacked class and the page says so; what the record can hold is G1 against the board class and the economics guard (capital per hash, the clock to a shipped machine) against the stacked and SRAM classes, which is the form the record's own class ruling of 10 October already had for the walk.

The lever that remains ours on energy is the GPU's own cost: R0C takes the 5090 from 12.2 to about 2.7 uJ per hash (the programme was a cost on the card alone), which is what lets the board class read under 3x; nothing further on the relation moves the stacked class, and the sizing's eight candidates (the four and the four here) are the record of that.

6. The ProgPoW class: a per-period programme of register-wide arithmetic compiled by the miner into the GPU's native instruction stream (the coordinator's order; the drawing board's one audited class)

The form: every N blocks the chain's state draws a programme of random register-wide integer operations (multiply, multiply-high, rotate, xor, add, popcount, count-leading-zeros) over a 32-register file with random source and destination registers (ProgPoW's KISS99 draw), which each miner compiles into its card's native instruction stream for the period; per round the programme runs on the lane's registers between the item read and the tree, the dependent walk kept at W256 for the memory term; the keyed rounds and pi unchanged. ProgPoW's own audits (Least Authority, 2019; the Kik analysis) put a specialist's edge on the programme at about 1.2x to 2x, because the chip must be a programmable core to execute an unbounded programme space, and the record's own model of that class (the SIMT-lane die of version8-c-terms.json: c 1.3 to 4.0, central 2.16, upper 4.99; the adjudicator's natively executed programme at 80 percent of the card's energy: 3.5x central, 2x to 6x) is the right model for THIS class, which is where the review's objection (the band charged an instruction stream to a wired programme) does not apply: the programme here is an instruction stream by construction, re-drawn every period, with register indices the chip cannot wire.

The reading: the ProgPoW class is the one form on the drawing board that reads at or under 3x central against the stacked class on the record's own figures (2.5x at share 0.8 on the record's c, 3.4x at share 0.5; 3.9x on the adjudicator's c), with the upper at 4.5x to 5.7x: at the target's edge, not past it. Its price is the GPU's own number: the card runs at 5.6 to 14 uJ per hash (the programme is a cost on the card at its native rate; the walk's 2.8 uJ is the floor), so "match or improve the current numbers" holds at share up to about 0.77 (14 uJ against 12.2) and the 4x gain of R0C is given up. The adversary's answer is the programmable core at c; what moves c toward 1.2x (ProgPoW's audits) or 4x (the record's upper) is the chip's register file and issue energy against the GPU's, and that is a placed-design question an in-house adversarial review's flow can read in the same night as the walk's engine (a lane with a 32-entry 2R1W file and a straight-line schedule store).

The one measurement tonight: a ProgPoW-shaped kernel on the 5090 pod at 500 W beside the walk (a team seat: a per-period programme of 64 and 256 random register operations per round over 32 registers, compiled into the kernel, the walk at W256; three 180 s windows each; the plug): the card's energy per hash and the programme's measured energy per instruction, which fixes the share and the card's number; the chip's side is the record's c band until the placed core reads.

The relation's owner's verdict on the drawing board: the ProgPoW class is the candidate to size on rows tonight as R0D (the matrix form reads 3x to 5x and splits the cohort; the ProgPoW class reads 2.5x to 3.9x central and keeps it); the sentence it can carry is "under 3x central against every class on the record's model of a programmable core, under 5x upper at the programme's share of 0.8", graded Hypothesis on c until the placed core reads, with the walk's measured memory classes beside it.

7. The three readings and the designers' columns

• The relation's owner (this page): no form reaches 3x against the stacked class; (i) reads 2x to 3x on the hot walk at the cost of the cohort and the clock guard; (ii) and (iii) move capital and empty the cohort; (iv) shrinks the station.
• An in-house adversarial review: confirms (i) to (iv) with its own figures ((i) 5x to 25x and no DRAM at all; (ii) the stack's capital per MH/s unchanged by size; (iii) inherits (i); (iv) a station is capacity); accepts 6.5x central at W256 as the stacked number and 2.0x to 2.4x the board's; adds the class (v), INT8 matrix MACs on the matrix units, at 3.7x to 4.8x central and about 5.5x upper on the stacked band (a figure main reports corrected to 5.4x central in an in-house adversarial review's later line), the cohort split and the verifier's 10 us named, "the nearest class and its price, not a candidate form"; its pipeline exact on both documents on a team machine with the walk-only parameter in.
• The edge adjudicator: confirms (i) to (iv) independently ((i) 6.8x central, 2.3x to 26x, worse than the board class; (ii) 0.05 to 0.4 USD per MH/s for a 24 GB bonded engine against the 5090's 49, capital does not bind; (iii) and (iv) no); names the stacked figure 6.5x central, 5.6x to 7.3x at W256 on the rows alone (8.7x at W128), with a full-SRAM 2 GiB die taking the energy upper to about 40x, so the served sentence rests on capital and clock for the stacked and SRAM classes and on energy only for the board class; corrects its own earlier per-bit slip (the boards are AT the GDDR6 floor, the X16-Q near bonded DRAM's); its R0C bound (board 2.6x central 1.5x to 5x; stack 6.5x central) is the stacked figure's grade on this page; the corrected adjudication at 5311b24ae084.
• Designer A: picks a dependent FP32 FMA chain (about 10^6 FMA per hash, 85 percent of the hash's energy, the working set in L2 and shared memory, one cold read, the keyed rounds and pi unchanged): the 5090 at 9.9 to 10.1 uJ per hash (DERIVED from the sheet FMA rate, 9.54 pJ per FMA at the cap), the cohort within 1.5x, FP32 FMA exact on three vendors under the fused round-to-nearest rule; the strongest feasible specialist at 1.7x central and at most 3.2x, every memory class alike, ON THE ADJUDICATION'S PER-INSTRUCTION TERMS (3.1 to 10 pJ, central 5.8); sizes the ProgPoW class beside it at 1.3x to 2.8x blended (central 1.8x) and keeps it as the fallback.
• One line of the record is not served here (a name, a machine or a path).

8. The relation's owner's reconciliation of the designers (by date)

1. The class (the coordinator's order on the project's line, "we are not measuring unlimited money, we are measuring with resources that Bitmain, Innosilicon and Jasminer have"): every headline figure below and on the R0D spec is read earliest against a leading-node GDDR board (the Bitmain and Innosilicon class) and the bonded stack (Jasminer's class) at the GPU's voltage class and those vendors' NRE and volumes; the near-threshold and full-SRAM figures are the unlimited class, disclosed, never the headline.

1. Designer A's 1.7x rests on the per-instruction engine the review broke this afternoon (the record's SIMT-lane terms applied to a chip that needs no register file and no issue for a FIXED chain); designer B's pipeline reading of the fixed FMA chain (3.3x central, 1.7x to 7x) is the one consistent with the day's concession, and its strong end breaches 5x. So the fixed chain is not the form.
2. The per-period PROGRAMME is what caps the chip's strong end (a programme re-drawn every period forbids the fully wired pipeline; the chip's strongest is a stripped core or a reconfigurable array at 2 to 3.5 pJ per op, not 1.3), and an FMA-heavy op set makes each op the dearest one the card issues at full rate on every vendor: that is the form both designers' columns point at from opposite chairs, and it is the relation's owner's pick for R0D's rows: the ProgPoW-class per-period programme over 32 registers with the op set weighted to FP32 FMA (with xor, rotate, add, multiply-high and a compiled range mask), the W256 walk kept, the keyed rounds and pi unchanged.
3. The number it reads against the strongest feasible chip at the GPU's own voltage class: 3.0x to 3.5x central (designer B's 3.6x at 500 W and 3.0x at a 400 W knee; this page's 2.5x on the record's c 2.16 is the optimistic end), 2x to 5x band, the strong end held under 5x by the period; against a chip with unbounded capital at near-threshold voltage, 4x to 8.5x (REPORTED class on the lever, not a shipped miner). It is not 2x; the project's "2 to 3x" is met at the central only against a chip at the GPU's voltage class, and the page says so.
4. The GPU's number on it: 10 to 12 uJ per hash at the 500 W cap at the programme's share of 0.8 to 0.85 (designer B's 11.5 to 12, designer A's 9.9 to 10.1 on the FMA floor): the current row's 12.2 matched, not improved; R0C's 2.7 is the form that improves it, at the stacked class's 6.5x.
5. The two kernels on the 5090 pod tonight settle the card's side (the pJ per native instruction on the programme and the pJ per FFMA on the chain, at 500 and 400 W, the instruction mix at 85 percent ALU and FMA, under 5 percent shuffle or select); the chip's side is two RTLs on an in-house adversarial review's flow (the stripped lane with a 32-entry file and a schedule store; the single FMA pipeline with a 64-word latch bank), the simplest engines named tonight. The pick between R0C and R0D is the coordinator's on those rows, with the relation's owner's reading that R0D at 3x central is the form the standard's G1 can carry against every class and R0C is not.