Six phases · updated 7 Oct 2026

The journey.

Six phases from the specification to a fair launch. Each closes at its gate, a measurement published whether it passes or fails, so there is no date to slip. Below the phases, the latest entries of the engineering log.

Under way; closes when the specification is out for external review
Under way

1. Specification

Mining generator, shard proving, finality rules, written for external review

Under way; closes at its gate
Under way

2. Prove the proving

Mining program proven on Apple, NVIDIA and AMD; shard proving benchmark on consumer cards still to run

Gate: A fixed published workload, job received to accepted proof on a declared consumer card, sustained with no growing backlog, reproduced by three independent operators

Devnet 3 live, testnet next
Under way

3. Devnet

Devnet 3 since 7 October 2026 with every upgrade on from block zero; GPU miners on three vendors; EVM execution and proving live

Gate: 1 block a second held with proofs under 60 s behind the tip

The log, newest first

Lately, in the log.

log

The first 16 GB card

The first 16 GB card: an RTX 5060 Ti in a Thunderbolt enclosure on the RTX 5090 Windows rig

log

Counter ASIC 3.0

Counter ASIC 3.0: the class v4 rehearsal

log

16:01Z: Ember run 6 on the three-card Windows rig

log

Counter ASIC 3.0 item 2

Counter ASIC 3.0 item 2: the per-day derivation

log

Counter ASIC 3.0 item 8

Counter ASIC 3.0 item 8: program work in the latency shadow

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Counter ASIC 3.0 item 6

Counter ASIC 3.0 item 6: the reserve families' step costs

log

Counter ASIC 3.0 gate run, the hash side

log

16:01Z: Ember run 6 on the three-card Windows rig (RTX 5090, RTX 4070

16:01Z: Ember run 6 on the three-card Windows rig (RTX 5090, RTX 4070, RX 9070 XT)

log

00:4xZ, the empty `/api/state` reply

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07:12Z to 07:17Z, the host's chain mode with --save-shards records…

07:12Z to 07:17Z, the host's chain mode with --save-shards records and --prev, on the Apple M5 Max's CPU

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07:52Z to 08:24Z, the segment-aligned prover beside the miner on the…

07:52Z to 08:24Z, the segment-aligned prover beside the miner on the RTX 5090 Windows rig's RTX 5090

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08:26Z to 08:35Z, the fast-time harness on the fresh-record rule

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12:25 to 13:20Z, the finality route: why 26 fresh nodes lost the…

12:25 to 13:20Z, the finality route: why 26 fresh nodes lost the seed every checkpoint

log

Ember Tune: the two-knob efficiency tune, the fleet prior

Ember Tune: the two-knob efficiency tune, the fleet prior, and what the three-card Windows rig could measure tonight

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The SP1 CPU prover on the three-card Windows rig beside the miners,…

The SP1 CPU prover on the three-card Windows rig beside the miners, and the backend survey: no zkVM proves on AMD

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The 9070 XT on the eGPU

The 9070 XT on the eGPU: why 17.9 MH/s, and what moved

log

Ember Tune: the two-knob efficiency tune, the fleet prior

Ember Tune: the two-knob efficiency tune, the fleet prior, and what the three-card Windows rig (RTX 5090, RTX 4070, RX 9070 XT) could measure tonight

log

Read width of the lottery hash

Read width of the lottery hash: 4, 16 and 64-byte loads, a per-load mix, a written scratch; three cards

log

The hot table on the M5 Max

The hot table on the M5 Max: a second table sized to GPU cache beside the 1 GiB dataset

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Mixer x4 and the cache growth rule

Mixer x4 and the cache growth rule: the class v3 dataset construction, with the x8 candidate

log

The SP1 CPU prover on the three-card Windows rig (RTX 5090, RTX…

The SP1 CPU prover on the three-card Windows rig (RTX 5090, RTX 4070, RX 9070 XT) beside the miners, and the backend survey: no zkVM proves on AMD

log

Proving v1: segment records, the chain rule

Proving v1: segment records, the chain rule, the unproven rule; what was measured tonight

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Dp4a-class throughput on the M5 Max

Dp4a-class throughput on the M5 Max: the dot4 emulation against the ALU chain

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Layer 3 scratch soundness

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Epoch length as an era parameter

Epoch length as an era parameter : the Apple M5 Max's compile-ahead per program

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Aggregation cost on the RTX 5090

Aggregation cost on the RTX 5090: what a per-block aggregation spends and what each lever gives

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The C4 fix: certificate-driven reorg

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EVM transaction relay

EVM transaction relay: three nodes in a chain, every transaction sent to one end included by the other two miners

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The prover carries both fee tables and the height switch

The prover carries both fee tables and the height switch: one pinned guest on either side of DAA 210,000

log

FUD ledger sweep round 6

log

Live devnet: real transactions, the first non-empty shard proven and…

Live devnet: real transactions, the first non-empty shard proven and paid, and the exporter's block structure fixed

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The program id split

The program id split: why the Apple M5 Max rejected the RTX 5090 Windows rig's proofs, and the verifier at 114 s

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Live devnet: the first shards proven, verified and paid

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Economy simulation: mining versus proving under stress

Sim/economy: mining versus proving under stress, agent-based

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Difficulty rule attacked seven ways

Difficulty rule under attack: pool hopping, pulsed rental, timestamp stretching, short-lane oscillation, epoch games, polluted window, block flood

log

Timestamp attack on the difficulty rule fixed

Difficulty rule: timestamp attack fixed , simulator regression, 3-node forger test

log

Devnet v4: nine branches merged into one node

Devnet-v4 integration: nine branches merged, 3-node test network on the merged node, Windows cross-build

log

Generator v2 adopted: every hash does 128 distinct reads

Generator version 2 adopted: exact load count, fresh-source loads, program acceptance; every vector re-cut, three workers re-checked, 20,000-program census, devnet-v4 binaries rebuilt

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First GPU proof of an Igneum block: 1.4 s on an RTX 5090

Proving v0 on the RTX 5090: first GPU proof of an Igneum block

log

Devnet v4 live: generator v2, two-thirds floor, fresh chain

Devnet v4 cut-over: generator v2, 2/3 floor, three nodes and a seed on a fresh chain

Every entry is a dated heading of the engineering log, where the commands and the hardware are. The phases and their gates are the litepaper’s roadmap.